1. Field of the Invention
The invention relates to a power-to-digital converter (PDC) and, in particular, to a small area PDC with high resolution.
2. Description of the Related Art
Power-to-digital converters (PDC) are often used in radio frequency (RF) communication systems. FIG. 1 is a block diagram of a conventional power-to-digital converter. The power-to-digital converter 100 receives and converts a signal power to digital codes. The power-to-digital converter 100 comprises a power detector 110 and an analog-to-digital converter (ADC) 120 coupled thereto. The power detector 110 receives the signal power and provides a DC output signal to the analog-to-digital converter 120. The analog-to-digital converter 120 converts the DC output signal of the power detector 110 to the digital codes. In such architecture, if the analog-to-digital converter 120 is an M-bit ADC, then the digital code has a resolution of M bits. In other words, an average resolution of the conventional power-to-digital converter is determined by a dynamic range (DR) of the power detector 110 and the bit resolution of the analog-to-digital converter 120, which is expressed as DR/2M. For example, a power detector with a dynamic range of 80 dBc and an 8-bit ADC is used in the conventional PDC. The PDC possesses 28 (256) available codes and an average resolution thereof is 80/28 (=0.31).
FIG. 2 is a schematic diagram of a conventional power detector in the conventional power-to-digital converter in FIG. 1. The power detector 200 comprises a plurality of amplifiers 210, a plurality of rectifiers 220, and a lower pass filter 230. Each rectifier 220 is coupled between an output of a respective amplifier 210 and the low pass filter 230. Since the power detector 200 requires a large number of amplifiers 210 and rectifiers 220, the power detector 200 occupies large area. In addition, a successive approximation (SAR) analog-to-digital converter (ADC) in the PDC having the power detector 200 in FIG. 2 covers all bit resolution required thereby. The SAR ADC requires a large number of resistors and capacitors. As a result, the resistor and capacitor arrays also occupy a large area. Accordingly, the conventional power-to-digital converter consumes a large silicon area due to a large power detector and a large SAR ADC.